Video Codec and Method thereof

ABSTRACT

A video codec method is provided, for processing video data processed by a Discrete Cosine Transformation (DCT) operation, comprising: (a) if a transformation matrix having a plurality of coefficients comprises at least one non-integer coefficient among the coefficients, multiplying the transformation matrix by a multiplication factor α to make all coefficients of the transformation matrix integers, (b) estimating a compensation set, (c) performing a Column in Row out IDCT two-dimensional operation on the video data according to the transformation matrix and the compensation set, to obtain a compensated two-dimension operation result, (d) selectively dividing the compensated two-dimension operation result by α 2  to obtain an IDCT operation result.

CROSS REFERENCE TO RELATED PATENT APPLICATION

This patent application is based on Taiwan, R.O.C. patent applicationNo. 099123693 filed on Jul. 19, 2010.

FIELD OF THE INVENTION

The present invention relates to a video codec and method thereof.

BACKGROUND OF THE INVENTION

A conventional structure of a multimedia application, such as a videocodec complying with H.264 specification, as shown in FIG. 1, includes aDiscrete Cosine Transformation (DCT) operation circuit 110, aQuantization (Q) unit 120, an Inverse Quantization (IQ) unit 130, and anInverse DCT (IDCT) operation circuit 140. The DCT operation circuit 110acts in a Row in Column out (R→C) mode, and the IDCT operation circuit140 also acts in a Row in Column out mode, and receives the output ofthe IQ unit 130.

In practice, the DCT operation circuit 110 and the IDCT operationcircuit 140 must operate complying with a specification, otherwisemismatch between an encoding path and a decoding path will occur,resulting in a “drifting” effect during video playback. However, in somecases, the R→C operation of the IDCT operation circuit 140 is notstraightforward in data flow, and a transposition is needed,accordingly. In addition, the prior art needs an extra buffer 135 tostore data temporarily, for transforming Column data outputted from theDCT operation circuit 110 into Row data to be inputted to the IDCToperation circuit 140, thereby leading to both increases in processingtime and cost of the video codec.

Therefore, an IDCT scheme for processing in a Column in Row out (C→R)mode, capable of real-time compensation, and requiring no extra bufferfor temporarily storing data, so as to reduce processing time and costin a video codec, is needed.

SUMMARY OF THE INVENTION

The present invention is aimed to provide a video codec and methodthereof, capable of performing an IDCT in a Column in Row out (C→R) modeas well as real-time compensation.

According to one embodiment, a video codec method is provided, forprocessing video data processed by a Discrete Cosine Transformation(DCT) operation, including: (a) if a transformation matrix having aplurality of coefficients comprises at least one non-integer coefficientamong the coefficients, multiplying the transformation matrix by amultiplication α to make all coefficients of the transformation matrixintegers, (b) estimating a compensation set, (c) performing a Column inRow out IDCT two-dimensional operation on the video data according tothe transformation matrix and the compensation set, to obtain acompensated two-dimension operation result, (d) selectively dividing thecompensated two-dimension operation result by α² to obtain an IDCToperation result.

According to another embodiment of the present invention, a video codecis provided, for processing video data processed by a Discrete CosineTransformation (DCT) operation, including: a DCT operation circuit, forperforming a Row in Column out IDCT operation on the video data, toobtain a DCT operation result, a quantization circuit and an inversequantization circuit, coupled to the DCT operation circuit, forperforming a quantization operation and an inverse quantizationoperation on the DCT operation result, an IDCT operation circuit,coupled to the inverse quantization circuit, for performing a Column inRow out IDCT operation on the output of the inverse quantization circuitto generate an IDCT operation result; and a compensation circuit,coupled to the IDCT operation circuit, for providing a compensation setto the IDCT operation circuit to compensate the IDCT operation result.

Following description and figures are disclosed to gain a betterunderstanding of the advantages of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a video codec supporting thespecification H.264 of the prior art.

FIG. 2 is a schematic diagram of a video codec according to anembodiment of the present invention.

FIG. 3A and FIG. 3B are respectively schematic diagrams of a Row inColumn out IDCT operation and a Column in Row out IDCT operation.

FIG. 4 illustrates an operation result of an IDCT operation circuit anda compensation unit, taking a matrix X^(t) as an input matrix.

FIG. 5A and FIG. 5B respectively illustrate two possible embodiments ofthe IDCT operation circuit in FIG. 2 according to an embodiment of thepresent invention.

FIG. 6, FIG. 7 and FIG. 8 illustrate a two-dimensional IDCTtransformation of a matrix, with a one-dimensional (1D) compensation setand a two-dimensional (2D) compensation set denoted respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In an embodiment of the present invention, column data outputted from aDCT operation circuit is inputted to a Column in Row out IDCT operationcircuit (i.e., an IDCT operation circuit acting in a Column in Row outmode); as a result, no additional buffer memory ahead of the IDCToperation circuit is needed. However, due to limitations of the numberof bits, an operation result of the Column in Row out IDCT operationcircuit may have some errors in response to an order inversion andround-off/carry-in operations. Thus, in the embodiment of the presentinvention, the errors are calculated in advance and corrected.

In mathematics theory (where the number of bits is unlimited), eitherthe IDCT operation circuit acts in the Row in Column out mode or in theColumn in Row out mode, the operation result should be identical.However, in practice, because the number of bits of the video codec islimited, if a fractional rounding operation is performed, the operationresult of the Column in Row out IDCT operation circuit may be differentfrom that of the Row in Column out IDCT operation circuit.

FIG. 2 is a function block diagram of a video codec according to anembodiment of the present invention. As shown in FIG. 2, the video codeccomprises: a DCT operation circuit 210, a quantization unit 220, aninverse quantization unit 230, an IDCT operation circuit 240, and acompensation unit 250. The compensation unit 250 inducts a compensationset Δ to an output of the IDCT operation circuit 240, for obtaining arequired correct result. Rounding mismatches resulted from an orderinversion can be real-time corrected by utilizing the compensation unit250, and circuit area of the compensation unit 250 is much less thanthat of the FIG. 1 required buffer 135.

In the H.264 specification, the two-dimensional (2D) IDCT transformationis defined as Y=TXT^(t).

FIG. 3A and FIG. 3B respectively illustrate the Row in Column out (R→C)IDCT operation and the Column in Row out (C→R) IDCT operation.Y^(t)=(TXT^(t))^(t)=TX^(t)T^(t)=Y′. In a floating-point operation inwhich the number of bits is unlimited, Y′ is equal to the transpositionresult of Y. However, in a design in which the number of bits islimited, if a transformation matrix T has at least a non-integercoefficient (such as ½), fraction rounding effects resulted from theorder inversion must be considered. A situation that the transformationmatrix T has non-integer coefficients is shown as follows:

$\underset{Y}{\begin{bmatrix}Y_{00} & Y_{01} & Y_{02} & Y_{03} \\Y_{10} & Y_{11} & Y_{12} & Y_{13} \\Y_{20} & Y_{21} & Y_{22} & Y_{23} \\Y_{30} & Y_{31} & Y_{32} & Y_{33}\end{bmatrix}} = {\underset{T}{\begin{bmatrix}1 & 1 & 1 & {1/2} \\1 & {1/2} & {- 1} & {- 1} \\1 & {{- 1}/2} & {- 1} & 1 \\1 & {- 1} & 1 & {{- 1}/2}\end{bmatrix}} \cdot \underset{X}{\begin{bmatrix}x_{00} & x_{01} & x_{02} & x_{03} \\x_{10} & x_{11} & x_{12} & x_{13} \\x_{20} & x_{21} & x_{22} & x_{23} \\x_{30} & x_{31} & x_{32} & x_{33}\end{bmatrix}} \cdot \underset{T^{\; t}}{\begin{bmatrix}1 & 1 & 1 & 1 \\1 & {1/2} & {{- 1}/2} & {- 1} \\1 & {- 1} & {- 1} & 1 \\{1/2} & {- 1} & 1 & {{- 1}/2}\end{bmatrix}}}$

In this situation, Y′ is not equal to the transposition result of Y(i.e., (Y′!=Y^(t))). That is to say, the transposition result of Y shownin FIG. 3A is not equal to Y′ shown in FIG. 3B.

Therefore, in the embodiment, when the matrix input order is invertedfrom X to X^(t), the following steps must be performed to correct theerrors.

(1) Firstly, changing the non-integer coefficients of the transformationmatrix into integer coefficients is performed. For example, in the aboveexample, multiplying the transformation matrix T by 2, so that thecoefficients (elements) of the obtained transformation matrix (2T) areall integers. Since the transformation matrix (2T) does not include anynon-integer coefficients, no error occurs even when fraction roundingoperations are performed. In regard to FIG. 3A and FIG. 3B,

Z=(2T)X(2T)^(t);

Z′=(2T)X ^(t)(2T)^(t);

and Z=(Z′)^(t).

(2) Since the number of bits is limited, in the embodiment, thecompensation set Δ is calculated in advance, according to transposesymmetry and a rule of the rounding operation. Therefore, a compensatedresult is determined as Y″=(Z′+Δ)/4.

(3) The compensated result Y″ may be regarded as the transpositionresult of the matrix Y, as if it is the two-dimensional (2D)transformation result of the matrix X (that is, as if it is the resultobtained by the Row in Column out IDCT). Therefore, the relationshipbetween the matrix Y″ and the matrix Y may be expressed as Y=(Y″)^(t).

Calculation of the compensation set Δ is depicted as follows.

In a fixed-point design, the result of right shifting the number X byone bit (that is, dividing the number X by 2 if the number X isexpressed in binary) is equal to the result of subtracting the LeastSignificant Bit (LSB) thereof from the number X and then dividing it by2. It can be expressed as following equation (a):

X _(>>1=½) X _(=½)(X−X[0])  (a)

Wherein, “X>>1” represents right shifting X by one bit, and X[0]represents the LSB of the number X.

In H.264 specification, the two-dimensional transformation of the Row inColumn out IDCT is defined as Y=TXT^(t).

Likewise, the two-dimensional transformation of the Column in Row outIDCT is defined as Y′=TX^(t)T^(t).

Using the coefficient Y₀₁ of the above matrix Y as an example, as shownin FIG. 6.

As in FIG. 6, a one-dimensional (1D) compensation set and atwo-dimensional (2D) compensation set are denoted respectively. The 1Dcompensation set and the 2D compensation set respectively include a setof coefficients of the matrix Y. The coefficient Y₀₁ can be expressedas:

Y₀₁ = x₀₀ + x₁₀ + x₂₀ + 1/2x₃₀ + (x₀₁ + x₁₁ + x₂₁ + 1/2x₃₁)(1/2) + (x₀₂ + x₁₂ + x₂₂ + 1/2x₃₂)(−1) + (x₀₃ + x₁₃ + x₂₃ + 1/2x₃₃)(−1)

Wherein, italic items belong to the 1D compensation set and boldfaceitems belong to the 2D compensation set. After substituting the equation(a) into the 1D compensation set of the Y₀₁ (i.e. ½X₃₀, ½X₃₁, ½X₃₂,½X₃₃), the Y₀₁ may be expressed as a combination of equations (b)˜(e):

$\begin{matrix}\begin{matrix}{Y_{01} = {x_{00} + x_{10} + x_{20} + {1/{2\left\lbrack {x_{30} - {x_{30}\lbrack 0\rbrack}} \right\rbrack}} +}} \\{{{\left( {x_{01} + x_{11} + x_{21} + {1/{2\left\lbrack {x_{31} - {x_{31}\lbrack 0\rbrack}} \right\rbrack}}} \right)\left( {1/2} \right)} +}} \\{{{\left( {x_{02} + x_{12} + x_{22} + {1/{2\left\lbrack {x_{32} - {x_{32}\lbrack 0\rbrack}} \right\rbrack}}} \right)\left( {- 1} \right)} +}} \\{{\left( {x_{03} + x_{13} + x_{23} + {1/{2\left\lbrack {x_{33} - {x_{33}\lbrack 0\rbrack}} \right\rbrack}}} \right)\left( {- 1} \right)}}\end{matrix} & \begin{matrix}(b) \\(c) \\(d) \\(e)\end{matrix}\end{matrix}$

When substituting equation (a) into equation (c) again, and simplifyingthe LSB of the 2D compensation set (X₀₁+X₁₁+X₂₁+(½) X₃₁) in equation (c)as X01[0] ̂X11[0]̂X21[0]̂X31[1], Y₀₁ may be expressed as follows:

$\begin{matrix}{Y_{01} = {x_{00} + x_{10} + x_{20} + {1/{2\left\lbrack {x_{30} - {x_{30}\lbrack 0\rbrack}} \right\rbrack}} + {\left( {x_{01} + x_{11} + x_{21} + {1/{2\left\lbrack {x_{31} - {x_{31}\lbrack 0\rbrack}} \right\rbrack}} - {{x_{01}\lbrack 0\rbrack}\hat{}{{x_{11}\lbrack 0\rbrack}\hat{}{{x_{21}\lbrack 0\rbrack}\hat{}{x_{31}\lbrack 1\rbrack}}}}} \right)\left( {1/2} \right)} + {\left( {x_{02} + x_{12} + x_{22} + {1/{2\left\lbrack {x_{32} - {x_{32}\lbrack 0\rbrack}} \right\rbrack}}} \right)\left( {- 1} \right)} + {\left( {x_{03} + x_{13} + x_{23} + {1/{2\left\lbrack {x_{33} - {x_{33}\lbrack 0\rbrack}} \right\rbrack}}} \right)\left( {- 1} \right)}}} & (f)\end{matrix}$

As Z is defined as Z=(2 T)X(2T)^(t), Z has no rounding effects,because the transformation matrix (2T) has no non-integer coefficients.

As shown in FIG. 7, the coefficient Z₀₁ of the matrix Z may be expressedas:

Z₀₁ = 4x₀₀ + 4x₁₀ + 4x₂₀ + 2x₃₀ + 2x₀₁ + 2x₁₁ + 2x₂₁ + 2x₃₁ − 4x₀₂ − 4x₁₂ − 4x₂₂ − 2x₃₂ − 4x₀₃ − 4x₁₃ − 4x₂₃ − 2x₃₃

As Z′ is defined as Z′=(2T)X^(t)(2T)^(t), Z′ also has no roundingeffects, because the transformation matrix (2T) has no non-integercoefficients, either.

As shown in FIG. 8, by comparison, it can be determined that Z′₁₀ isequal to Z₀₁ (i.e. Z′=Z^(t)).

$\begin{matrix}{Z_{10}^{\prime} = {{4x_{00}} + {4x_{10}} + {4x_{20}} + {2x_{30}} +}} \\{{{2x_{01}} + {2x_{11}} + {2x_{21}} + x_{31} -}} \\{{{4x_{02}} - {4x_{12}} - {4x_{22}} - {2x_{32}} -}} \\{{{4x_{03}} - {4x_{13}} - {4x_{23}} - {2x_{33}}}} \\{= Z_{01}}\end{matrix}$

After scaling up the matrix Y by 4 times, the relationship between Y₁₀and Z′₁₀ may be expressed as:

In the above expression, (−2X₃₀[0]−X₃₁[0]+2X₃₂[0]+2X₃₃[0]) representsthe 1D compensation set, and (−2X₀₁[0]̂X₁₁[0]̂X₂₁[0]̂X₃₁[0]) represents the2D compensation set.

As described above, the following steps, concluded from the above, areutilized for compensation of mismatch resulted from the order inversion(i.e. changing the IDCT from the Row in Column out mode to the Column inRow out mode).

(1) Changing non-integer coefficients of the transformation matrix intointeger coefficients is performed. For example, in the above example,multiplying the transformation matrix by 2, such that the coefficientsof the obtained transformation matrix are all integers. Therefore, noerrors occur even when fractional rounding operations are performed.

Z=(2T)X(2T)^(t);

Z′=(2T)X ^(t)(2T)^(t);

and Z=(Z′)^(t).

(2) Since the number of bits is limited, calculating the compensationset Δ in advance (according to transpose symmetry and the rule of therounding operation) is performed. Then, the compensated result isdetermined to be Y″=(Z′+Δ)/4.

(3) The compensated result Y″ may be regarded as the transpositionresult of the matrix Y, as if it is the two-dimensional (2D)transformation result of the matrix X (that is, as if it is the resultobtained by the Row in Column out IDCT). Therefore, the relationshipbetween the matrix Y″ and the matrix Y may be expressed as Y=(Y″)^(t).That is, Y=(Z′+Δ_(—)1D+Δ_(—)2D)^(t)/4=(Z′+Δ)^(t)/4, wherein, Δ_(—)1Drepresents the one-dimensional compensation set, and Δ_(—)2D representsthe two-dimensional compensation set.

Referring to FIG. 4, taking the matrix X^(t) as an input matrix, theIDCT operation circuit performs the operation of Z′=(2T)X^(t)(2T)^(t),for obtaining Z′. Subsequently, after performing the compensation(adding Δ and being divided by 4) and the transposition, the matrix Ycan be obtained. That is to say, Y=((Z′+Δ)/4)^(t). This operation isperformed by the compensation unit.

With the above deducing process, it can be concluded that theone-dimensional compensation set (may be named as Δ_(—)1D or 1D-term)and the two-dimensional compensation set (may be named as Δ_(—)2D or2D-term) are respectively expressed as follows:

${1D\text{-}{term}} = \begin{bmatrix}{{{- 2}{x_{30}\lbrack 0\rbrack}} - {2{x_{31}\lbrack 0\rbrack}} - {2{x_{32}\lbrack 0\rbrack}} - {x_{33}\lbrack 0\rbrack}} & \ldots & \ldots & \ldots \\{{{- 2}{x_{30}\lbrack 0\rbrack}} - {x_{31}\lbrack 0\rbrack} + {2{x_{32}\lbrack 0\rbrack}} + {2{x_{33}\lbrack 0\rbrack}}} & \ldots & \ldots & \ldots \\{{{- 2}{x_{30}\lbrack 0\rbrack}} + {x_{31}\lbrack 0\rbrack} + {2{x_{32}\lbrack 0\rbrack}} - {2{x_{33}\lbrack 0\rbrack}}} & \ldots & \ldots & \ldots \\{{{- 2}{x_{30}\lbrack 0\rbrack}} + {2{x_{31}\lbrack 0\rbrack}} - {2{x_{32}\lbrack 0\rbrack}} + {x_{33}\lbrack 0\rbrack}} & \ldots & \ldots & \ldots\end{bmatrix}$ ${2D\text{-}{term}} = \begin{bmatrix}{{- 2}{{x_{03}\lbrack 0\rbrack}\hat{}{{x_{13}\lbrack 0\rbrack}\hat{}{{x_{23}\lbrack 0\rbrack}\hat{}{x_{33}\lbrack 1\rbrack}}}}} & \ldots & \ldots & \ldots \\{{- 2}{{x_{01}\lbrack 0\rbrack}\hat{}{{x_{11}\lbrack 0\rbrack}\hat{}{{x_{21}\lbrack 0\rbrack}\hat{}{x_{31}\lbrack 1\rbrack}}}}} & \ldots & \ldots & \ldots \\{{+ 2}x\; {{01\lbrack 0\rbrack}\hat{}{{x_{11}\lbrack 0\rbrack}\hat{}{{x_{21}\lbrack 0\rbrack}\hat{}{x_{31}\lbrack 1\rbrack}}}}} & \ldots & \ldots & \ldots \\{{+ 2}{{x_{03}\lbrack 0\rbrack}\hat{}{{x_{13}\lbrack 0\rbrack}\hat{}{{x_{23}\lbrack 0\rbrack}\hat{}{x_{33}\lbrack 1\rbrack}}}}} & \ldots & \ldots & \ldots\end{bmatrix}$1D-term₀₀ = −2x₃₀[0] − 2x₃₁[0] − 2x₃₂[0] − x₃₃[0]1D-term₁₀ = −2x₃₀[0] − x₃₁[0] + 2x₃₂[0] + 2x₃₃[0]1D-term₂₀ = −2x₃₀[0] + x₃₁[0] + 2x₃₂[0] − 2x₃₃[0]1D-term₃₀ = −2x₃₀[0] + 2x₃₁[0] − 2x₃₂[0] + x₃₃[0] … … … …${2D\text{-}{term}_{00}} = {{- 2}{{x_{03}\lbrack 0\rbrack}\hat{}{{x_{13}\lbrack 0\rbrack}\hat{}{{x_{23}\lbrack 0\rbrack}\hat{}{x_{33}\lbrack 1\rbrack}}}}}$${2D\text{-}{term}_{10}} = {{- 2}{{x_{01}\lbrack 0\rbrack}\hat{}{{x_{11}\lbrack 0\rbrack}\hat{}{{x_{21}\lbrack 0\rbrack}\hat{}{x_{31}\lbrack 1\rbrack}}}}}$${2D\text{-}{term}_{20}} = {{+ 2}x\; {{01\lbrack 0\rbrack}\hat{}{{x_{11}\lbrack 0\rbrack}\hat{}{{x_{21}\lbrack 0\rbrack}\hat{}{x_{31}\lbrack 1\rbrack}}}}}$${2D\text{-}{term}_{30}} = {{+ 2}{{x_{03}\lbrack 0\rbrack}\hat{}{{x_{13}\lbrack 0\rbrack}\hat{}{{x_{23}\lbrack 0\rbrack}\hat{}{x_{33}\lbrack 1\rbrack}}}}}$… … … …

FIG. 5A and FIG. 5B respectively illustrate two possible implementationsof the IDCT operation circuit 240 according to embodiments of thepresent invention. In FIG. 5A, the compensation unit 242 performs aone-dimensional compensation set compensation operation on the output ofthe column IDCT operation circuit 241, and the compensation unit 246performs a two-dimensional compensation set compensation operation onthe output of the row IDCT operation circuit 245. A transposition memory243 is disposed between the column IDCT operation circuit 241 and therow IDCT operation circuit 245. From the above descriptions, the detailoperations of the column IDCT operation circuit 241 and the row IDCToperation circuit 245 are familiar to those skilled in the art, and areomitted herein.

As shown in FIG. 5B, the compensation unit 250 performs theone-dimensional compensation set compensation operation and thetwo-dimensional compensation set compensation operation on the output ofthe Row IDCT operation circuit 245 directly. The 1D-term and 2D-termlisted in the above equations may respectively represent theone-dimensional compensation set and the two-dimensional compensationset in FIG. 5B. The one-dimensional compensation set Δ_(—)1D and thetwo-dimensional compensation set Δ_(—)2D in FIG. 5A can be deduced fromthe above descriptions by those skilled in the art, and the detaileddescriptions are omitted herein.

Although the compensation set is calculated by the above expressions, inother specifications, different transformation matrixes may be adopted.According to the above descriptions of the present invention, as todifferent specifications and different transformation matrixes, thepresent invention is also applicable. That is, changing all of thenon-integer coefficients of the transformation matrix into integercoefficients (such as scaling up) for avoiding the mismatch resultedfrom a fixed-point calculation. Then, substituting compensation setsinto the matrix according to the rounding operating principle and thetransposing principle. Afterwards, transposing the matrix obtained byscaling down an operation result of the above steps, so as to acquire arequired correct result.

In addition, although the above embodiment takes multiplying thetransformation matrix by 2 as an example, the present invention is notlimited to this. In other possible embodiments of the present invention,it can multiply all of the coefficients of the transformation matrix byα, such that all coefficients are integers, and divide the operationresult by α².

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not to be limited to the aboveembodiments. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

1. A video codec method, for processing video data processed by aDiscrete Cosine Transformation (DCT) operation, comprising: (a) if atransformation matrix having a plurality of coefficients comprises atleast one non-integer coefficient among the coefficients, multiplyingthe transformation matrix by a multiplication factor α to make allcoefficients of the transformation matrix integers; (b) estimating acompensation set; (c) performing a Column in Row out IDCTtwo-dimensional operation on the video data according to thetransformation matrix and the compensation set, to obtain a compensatedtwo-dimension operation result; and (d) selectively dividing thecompensated two-dimension operation result by α² to obtain an IDCToperation result.
 2. The video codec method of claim 1, wherein step ofselectively dividing the compensated two-dimension operation result byα² to obtain an IDCT operation result comprises: if the transformationmatrix is multiplied in the step (a), dividing the compensatedtwo-dimension operation result by α² to obtain an IDCT operation result;and if the transformation matrix is not multiplied in the step (a),applying the compensated two-dimension operation result as the IDCToperation result.
 3. The video codec method of claim 1, wherein thecompensation set comprises a one-dimension compensation set and atwo-dimension compensation set, the step (c) comprises: performing theColumn in Row out IDCT two-dimensional operation according to thetransformation matrix without the compensation set, to obtain anuncompensated two-dimension operation result; and performing acompensation of the one-dimension compensation set and that of thetwo-dimension compensation set on the uncompensated two-dimensionoperation result, to obtain the compensated two-dimension operationresult.
 4. The video codec method of claim 1, wherein the compensationset comprises a one-dimension compensation set and a two-dimensioncompensation set, the step (c) comprises: performing a column IDCToperation on the video data to obtain a column IDCT operation result;performing a compensation of the one-dimension compensation set on thecolumn IDCT operation result, to obtain a compensated column IDCToperation result; performing a row IDCT operation on the compensatedcolumn IDCT operation result, to obtain a row IDCT operation result; andperforming a compensation of the two-dimension compensation set on therow IDCT operation result, to obtain the compensated two-dimensionoperation result.
 5. A video codec, for processing video data processedby a Discrete Cosine Transformation (DCT) operation, comprising: a DCToperation circuit, for performing a Row in Column out IDCT operation onthe video data, to obtain a DCT operation result; a quantization circuitand an inverse quantization circuit, coupled to the DCT operationcircuit, for performing a quantization operation and an inversequantization operation on the DCT operation result; an IDCT operationcircuit, coupled to the inverse quantization circuit, for performing aColumn in Row out IDCT operation on the output of the inversequantization circuit to generate an IDCT operation result; and acompensation circuit, coupled to the IDCT operation circuit, forproviding a compensation set to the IDCT operation circuit to compensatethe IDCT operation result.
 6. The video codec of claim 5, wherein thecompensation set comprises a one-dimension compensation set and atwo-dimension compensation set, the compensation circuit performs acompensation of the one-dimension compensation set and that of thetwo-dimension compensation set on the output of the IDCT operationcircuit, to obtain the IDCT operation result.
 7. The video codec ofclaim 5, wherein the IDCT operation circuit comprises a column IDCToperation unit and a row IDCT operation unit, the compensation circuitcomprises a first compensation unit and a second compensation unit, thecompensation set comprises a one-dimension compensation set and atwo-dimension compensation set.
 8. The video codec of claim 7, wherein:the column IDCT operation unit performs a column IDCT operation on thevideo data to obtain a column IDCT operation result; the firstcompensation unit is coupled to the column IDCT operation unit, forperforming a compensation of the one-dimension compensation set on thecolumn IDCT operation result, to obtain a compensated column IDCToperation result; the row IDCT operation unit performs a row IDCToperation on the compensated column IDCT operation result, to obtain arow IDCT operation result; and the second compensation unit is coupledto the row IDCT operation unit, for performing a compensation of thetwo-dimension compensation set on the row IDCT operation result, toobtain the compensated two-dimension operation result.